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Verification Intelligence Platform Agents

Discover the specialized, purpose-built agents that automate the most tedious aspects of Design Verification.

Testplan Generation
Test Generation
Change Impact
Focused Regression
Brain

Shared Project Context

All agents share a unified semantic model of your design.

Traceability
Formal Verification
Bug/Jira Sync
Coverage Signoff

01 Regression / RCA Agent

Turn regression noise into an evidence-backed root-cause investigation.

~/veriquest/rca

The Problem

Engineers spend hours manually digging through massive regression logs, and tracing signal failures back through complex logic hierarchies is tedious and requires deep design knowledge.

Inputs

Simulation log files (`sim_logs/`), RTL (`rtl/`), Testbench (`tb/`).

Analysis

AI processing & correlation

Outputs

Parsed JSON failure summaries and Markdown RCA reports citing exact root causes.

Business Value

Reduces regression analysis and debugging time from hours to minutes by providing an evidence-checked explanation of the failure mechanism.

Capabilities

cluster failures

localize root cause

classify RTL vs. TB

correlate Git / history

suggest fixes

focus validation

02 Coverage Closure Agent

Turn uncovered coverage into an actionable closure plan.

~/veriquest/coverage

The Problem

Closing the final 5% of coverage takes disproportionately long due to hard-to-hit edge cases.

Inputs

Coverage databases (`coverage_reports/`), RTL.

Analysis

AI processing & correlation

Outputs

Coverage closure report and actionable gap recommendations JSON.

Business Value

Eliminates the guesswork in coverage closure, reducing the time spent writing redundant tests.

Capabilities

analyze merged coverage

find missing bins / branches

link RTL and stimulus

diagnose gap causes

recommend tests

focus validation

03 Assertion Agent

Turn design intent into executable properties.

~/veriquest/assertion

The Problem

Writing correct, efficient SVAs is a specialized skill that is prone to syntax and logic errors.

Inputs

Specification PDFs (`docs/spec.pdf`), Assertion requirements (`dv.md`).

Analysis

AI processing & correlation

Outputs

Assertion plan JSON/MD, and bindable SystemVerilog (`{project}_assertions.sv`).

Business Value

Ensures comprehensive protocol and safety checking without the manual SVA coding overhead.

Capabilities

analyze spec and RTL

identify property needs

generate assertion plan

generate SVA + bind

compile and activate

analyze results

04 Chat Assistant Agent

Provide a conversational interface to the Verification Brain.

~/veriquest/orchestration

The Problem

Knowledge is siloed between logs, specs, and generated reports.

Inputs

All project KBs, generated reports, logs.

Analysis

AI processing & correlation

Outputs

Context-aware answers in the CLI.

Business Value

Provides an always-available expert assistant that understands your specific design and its current verification status.

Capabilities

ask project questions

retrieve grounded answers

show source evidence

navigate project history

explain Brain context

invoke specialist agents